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CS5361 114 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture 24-Bit Conversion 114 dB Dynamic Range -105 dB THD+N System Sampling Rates up to 192 kHz Less than 150 mW Power Consumption High Pass Filter or DC Offset Calibration Supports Logic Levels Between 5 and 2.5V Differential Analog Architecture Linear Phase Digital Anti-Alias Filtering Overflow Detection
General Description
The CS5361 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24bit values for both left and right inputs in serial form at sample rates up to 192 kHz per channel. The CS5361 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADC uses a differential architecture which provides excellent noise rejection. The CS5361 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors. ORDERING INFORMATION CS5361-KS -10 to 70 C 24-pin SOIC CS5361-BS -40 to 85 C 24-pin SOIC CS5361-KZ -10 to 70 C 24-pin TSSOP CS5361-BZ -40 to 85 C 24-pin TSSOP CDB5361 Evaluation Board
VQ
REFGND
OVFL
VL SCLK
LRCK SDOUT
MCLK
FILT+
Voltage Reference
Serial Output Interface
RST I2S/LJ M/S High Pass Filter HPF MDIV
AINLAINL+ S/H
+ -
LP Filter
Digital Decimation Filter
DAC AINRAINR+ S/H + LP Filter Digital Decimation Filter High Pass Filter MODE0 MODE1
DAC
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
AUG `02 DS467PP2 1
CS5361
TABLE OF CONTENTS
1 PIN DESCRIPTIONS ................................................................................................................. 4 2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 5 3 APPLICATIONS ......................................................................................................................... 6 3.1 Operational Mode/Sample Rate Range Select .................................................................. 6 3.2 System Clocking ................................................................................................................ 6 3.2.1 Master Mode ......................................................................................................... 7 3.2.2 Slave Mode ........................................................................................................... 8 3.3 Power-up Sequence .......................................................................................................... 8 3.4 Analog Connections ........................................................................................................... 8 3.5 High Pass Filter and DC Offset Calibration ....................................................................... 9 3.6 Overflow Detection ............................................................................................................. 9 3.6.1 OVFL Output Timing ........................................................................................... 10 3.7 Grounding and Power Supply Decoupling ....................................................................... 10 3.8 Synchronization of Multiple Devices ................................................................................ 10 4 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 11 ANALOG CHARACTERISTICS (CS5361-KS/KZ) .................................................................. 11 ANALOG CHARACTERISTICS (CS5361-BS/BZ) .................................................................. 12 DIGITAL FILTER CHARACTERISTICS.................................................................................. 13 DC ELECTRICAL CHARACTERISTICS................................................................................. 16 DIGITAL CHARACTERISTICS ............................................................................................... 16 THERMAL CHARACTERISTICS............................................................................................ 17 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 17 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 18 5 PARAMETER DEFINITIONS ................................................................................................... 21 6 PACKAGE DIMENSIONS ..................................................................................................... 22 7 ADDENDUM ............................................................................................................................ 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRNOMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
CS5361
LIST OF FIGURES
Figure 1. Typical Connection Diagram............................................................................................ 5 Figure 2. CS5361 Master Mode Clocking ....................................................................................... 7 Figure 3. CS5361 Recommended Analog Input Buffer................................................................... 9 Figure 4. Single Speed Mode Stopband Rejection ....................................................................... 14 Figure 5. Single Speed Mode Transition Band ............................................................................. 14 Figure 6. Single Speed Mode Transition Band (Detail)................................................................. 14 Figure 7. Single Speed Mode Passband Ripple ........................................................................... 14 Figure 8. Double Speed Mode Stopband Rejection...................................................................... 14 Figure 9. Double Speed Mode Transition Band ............................................................................ 14 Figure 10. Double Speed Mode Transition Band (Detail) ............................................................. 15 Figure 11. Double Speed Mode Passband Ripple ........................................................................ 15 Figure 12. Quad Speed Mode Stopband Rejection ...................................................................... 15 Figure 13. Quad Speed Mode Transition Band............................................................................. 15 Figure 14. Quad Speed Mode Transition Band (Detail) ................................................................ 15 Figure 15. Quad Speed Mode Passband Ripple........................................................................... 15 Figure 16. Master Mode, Left Justified SAI ................................................................................... 19 Figure 17. Slave Mode, Left Justified SAI ..................................................................................... 19 Figure 18. Master Mode, I2S SAI .................................................................................................. 19 Figure 19. Slave Mode, I2S SAI .................................................................................................... 19 Figure 20. OVFL Output Timing .................................................................................................... 19 Figure 21. Left Justified Serial Audio Interface ............................................................................. 20 Figure 22. I2S Serial Audio Interface............................................................................................. 20 Figure 23. OVFL Output Timing, I2S Format ................................................................................ 20 Figure 24. OVFL Output Timing, Left-Justified Format ................................................................. 20 Figure 25. CS5351/CS5361 Analog Input Buffer .......................................................................... 24
LIST OF TABLES
Table 1. CS5361 Mode Control ............................................................................................................. 6 Table 2. CS5361 Common Master Clock Frequencies ........................................................................ 7 Table 3. CS5361 Slave Mode Clock Ratios .......................................................................................... 8
3
CS5361
1 PIN DESCRIPTIONS
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I2S/LJ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VQ AINR+ AINRVA GND AINLAINL+ OVFL M1 M0
Pin Name
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I2 S/LJ
# 1 2 3 4 5 6 8 9 10 11 12
Pin Description
Reset (Input) - The device enters a low power mode when low. Master/Slave Mode (Input) - Selects operation as either clock master or slave. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section.
7,18 Ground (Input) - Ground reference. Must be connected to analog ground.
Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two's complement serial audio data. MCLK Divider (Input) - Enables a master clock divide by two function. High Pass Filter Enable (Input) - Enables the Digital High-Pass Filter. Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.
M0 M1 OVFL AINL+ AINLVA AINRAINR+ VQ REF_GND FILT+
13, Mode Selection (Input) - Determines the operational mode of the device. 14 15
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
16, Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma 17 modulators via the AINL+/- pins. 19
Analog Power (Input) - Positive power supply for the analog section.
20, Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma 21 modulators via the AINR+/- pins. 22 23 24
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
4
CS5361
2 TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V
+ 1 F
0.1 F
0.1 F
+
+5V to 2.5V
1 F
+5V
+
1 F
0.1 F
5.1
0.1 F
VA FILT+
47 F
VD
VL VL
+
0.1 F
REFGND +
1 F 0.1 F
10 k OVFL RST I2S/LJ M/S HPF M0 M1 MDIV Power Down and Mode Settings
VQ
Analog Input Buffer (Figure 3)
AINL+
CS5361 A/D CONVERTER
AINLSDOUT Audio Data Processor
Analog Input Buffer (Figure 3)
AINR+
LRCK SCLK MCLK Timing Logic and Clock
AINR-
GND
GND
Figure 1. Typical Connection Diagram
5
CS5361
3 APPLICATIONS 3.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2kHz to 192kHz. The CS5361 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 1.
M1 (Pin 14) M0 (Pin 13) 0 0 0 1 1 0 1 1
MODE Single Speed Mode Double Speed Mode Quad Speed Mode Reserved
Output Sample Rate (Fs) 2kHz - 50kHz 50kHz - 100kHz 100kHz - 192kHz
Table 1. CS5361 Mode Control
3.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0.
6
CS5361
3.2.1 Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 2. Refer to Table 2 for common master clock frequencies.
/ 256 / 128 / 64 /1 MCLK /2 1 /4 MDIV /2 /1
Single Speed Double Speed Quad Speed Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
0 M1 M0
00 01 10
SCLK Output
Figure 2. CS5361 Master Mode Clocking
SAMPLE RATE (kHz) 32 44.1 48 64 88.2 96 176.4 192
MDIV = 0 MCLK (MHz) 8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288
MDIV = 1 MCLK (MHz) 16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576
Table 2. CS5361 Common Master Clock Frequencies
7
CS5361
3.2.2 Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3 for required clock ratios.
Single Speed Mode Fs = 2kHz to 50kHz MCLK/LRCK Ratio SCLK/LRCK Ratio 256x, 512x 32x, 64x, 128x Double Speed Mode Fs = 50kHz to 100kHz 128x, 256x 32x, 64x Quad Speed Mode Fs = 100kHz to 192kHz 128x, 256x 64x
Table 3. CS5361 Slave Mode Clock Ratios
3.3
Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance.
3.4
Analog Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3 which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Please see the Addendum at the end of the datasheet for an analog input buffer that can be used with both the CS5351 as well as the CS5361 with a simple change in the bill of materials.
8
CS5361
634
470 pF COG 100 uF AIN+ 10 k COG VQ 10 k 100 uF AIN+ 470 pF COG 634 91 CS5361 AIN2700 pF + 91 CS5361 AIN+
Figure 3. CS5361 Recommended Analog Input Buffer
3.5
High Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5361 may generate a small DC offset into the A/D converter. The CS5361 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS5361 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5361.
3.6
Overflow Detection
The CS5361 includes overflow detection on both the left and right channels. This time multiplexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a logical low as soon as an overrange condition in either channel is detected. The data will remain low
9
CS5361
as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any other overrange condition detected. Please note that an overrange condition on either channel will restart the timeout period for both channels.
3.6.1
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow status. In I2S format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
3.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5361 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB5361 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
3.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5361's in the system. If only one master clock source is needed, one solution is to place one CS5361 in Master mode, and slave all of the other CS5361's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5361 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
10
CS5361
4 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (CS5361-KS/KZ) (Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Typical performance characteristics are derived from measurements taken at TA = 25C, VL = VD = 3.3V and VA = 5.0V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.) Parameter Fs = 48kHz A-weighted unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Quad Speed Mode Fs = 192kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage (at VA = 5V) Input Impedance (Differential) (Note 2) Common Mode Rejection Ratio Single Speed Mode Dynamic Range Symbol Min 108 105 THD+N 108 105 THD+N 108 105 THD+N 1.9 37 -105 -91 -51 -102 110 0.0001 0.1 -99 dB dB dB dB dB Degree dB % ppm/C LSB LSB Vrms k dB -105 -91 -51 -102 114 111 108 -99 dB dB dB dB dB dB dB -105 -91 -51 114 111 108 -99 dB dB dB dB dB dB Typ 114 111 Max Unit dB dB
100
0 100 2.0 82
5
2.1 -
CMRR
Notes: 1. Referred to the typical full-scale input voltage.
11
CS5361
ANALOG CHARACTERISTICS (CS5361-BS/BZ) ((Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Typical performance characteristics are derived from measurements taken at TA = 25C, VL = VD = 3.3V and VA = 5.0V. Min/Max performance characteristics are guaranteed over the specified operating temperature and voltages.)
Parameter Single Speed Mode Dynamic Range Fs = 48kHz A-weighted unweighted Total Harmonic Distortion + Noise -1 dB -20 dB -60 dB Double Speed Mode Fs = 96kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Quad Speed Mode Fs = 192kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage (at VA = 5V) Input Impedance (Differential) (Note 2) Common Mode Rejection Ratio Measured between AIN+ and AINSymbol Min 106 103 THD+N 106 103 THD+N 106 103 THD+N 1.8 37 -105 -91 -51 -102 110 0.0001 0.1 -97 dB dB dB dB dB Degree dB % ppm/C LSB LSB Vrms k dB -105 -91 -51 -102 114 111 108 -97 dB dB dB dB dB dB dB -105 -91 -51 114 111 108 -97 dB dB dB dB dB dB Typ 114 111 Max Unit dB dB
100
0 100 2.0 82
5
2.2 -
CMRR
Notes: 2.
12
CS5361
DIGITAL FILTER CHARACTERISTICS
Parameter Single Speed Mode (2kHz to 50kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Double Speed Mode (50kHz to 100kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Quad Speed Mode (100kHz to 192kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 3. The filter frequency response scales precisely with Fs. 4. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. -3.0 dB -0.13 dB @ 20Hz (Note 4) (Note 4) 1 20 10 105/Fs 0 Hz Hz Deg dB s tgd tgd (Note 3) (-0.1 dB) (Note 3) 0 0.78 -97 5/Fs 0.24 0.035 0.0 Fs dB Fs dB s s tgd tgd (Note 3) (-0.1 dB) (Note 3) 0 0.68 -92 9/Fs 0.45 0.035 0.0 Fs dB Fs dB s s tgd tgd (Note 3) (-0.1 dB) (Note 3) 0 0.58 -95 12/Fs 0.47 0.035 0.0 Fs dB Fs dB s s Symbol Min Typ Max Unit
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CS5361
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 4. Single Speed Mode Stopband Rejection
0 -1 -2
Figure 5. Single Speed Mode Transition Band
0.10
0.08
0.05
-3 -4 -5 -6 -7 -8 -9 -10 0.45
Amplitude (dB)
0.03 Amplitude (dB)
0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
0.00
-0.03
-0.05
-0.08
Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 6. Single Speed Mode Transition Band (Detail)
0 -10 -20 -30 -40 -50 Amplitude (dB)
Figure 7. Single Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
-60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 8. Double Speed Mode Stopband Rejection
Figure 9. Double Speed Mode Transition Band
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CS5361
0 -1 -2
0.10
0.08
0.05
-3 -4 -5 -6 -7 -8 -9 -10 0.40
Amplitude (dB)
0.03 Amplitude (dB)
0.43 0.45 0.48 Frequency (normalized to Fs) 0.50 0.53 0.55
0.00
-0.03
-0.05
-0.08
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 10. Double Speed Mode Transition Band (Detail)
Figure 11. Double Speed Mode Passband Ripple
0 -10 -20 -30 -40 Amplitude (dB)
Amplitude (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80
-50 -60 -70 -80 -90 -100 -110 -120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
-90 -100 -110 -120 -130 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Frequency (normalized to Fs)
Figure 12. Quad Speed Mode Stopband Rejection
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 Frequency (normalized to Fs)
Figure 13. Quad Speed Mode Transition Band
0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00
Amplitude (dB)
Amplitude (dB)
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 14. Quad Speed Mode Transition Band (Detail)
Figure 15. Quad Speed Mode Passband Ripple
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CS5361
DC ELECTRICAL CHARACTERISTICS (GND = 0V, all voltages with respect to ground.
MCLK=12.288 MHz; Master Mode) Parameter DC Power Supplies: Positive Analog Positive Digital Positive Logic VA VL,VD = 5 V VL,VD = 3.3V VA VL,VD=5V VL, VD=5V VL, VD = 3.3V (Power-Down Mode) (Note 6) Symbol VA VD VL IA ID ID IA ID PSRR Min 4.75 3.1 2.37 Typ 5.0 17.5 22 14.5 2 2 198 135 20 65 2.5 25 0.01 5 18 0.01 Max 5.25 5.25 5.25 21 26 17 235 161 Unit V V V mA mA mA mA mA mW mW mW dB V
Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode)(Note 5) Power Consumption (Normal Operation)
Power Supply Rejection Ratio (1 kHz) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
k
mA V
k
mA
Notes: 5. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 6. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 100 uA Low-Level Output Voltage at Io = 100 uA OVFL Current Sink Input Leakage Current (% of VL) (% of VL) (% of VL) (% of VL) Symbol VIH VIL VOH VOL Iovfl Iin Min 70% 70% Typ Max 30% 15% 4.0 10 Units V V V V mA A
16
CS5361
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance Ambient Operating Temperature (Power Applied) -KS -BS Symbol Min -10 -40 Typ 70 Max 135 +70 +85 Unit C C/W C C
JA
TA TA
ABSOLUTE MAXIMUM RATINGS (GND = 0V, All voltages with respect to ground.) (Note 7)
Parameter DC Power Supplies: Analog Logic Digital (Note 8) (Note 9) (Note 9) Symbol VA VL VD Iin VIN VIND TA Tstg Min -0.3 -0.3 -0.3 GND-0.7 -0.7 -50 -65 Typ Max +6.0 +6.0 +6.0 10 VA+0.7 VL+0.7 +95 +150 Units V V V mA V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 7. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 8. The maximum over/under voltage is limited by the input current. 9. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
17
CS5361
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL = 1.7V to 5.25V, VA = 5V5%, VD = 3.1V to 5.25V, CL = 20 pF) Parameter Input Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs tsetup thold Min 2 50 100 16/fsclk 1/fsclk tclkw tclkh tclkl tmslr tsdo 40 15 15 -20 0 Typ 740 680 50 50 Max 50 100 192 1953 20 40 Unit kHz kHz kHz s s ms ms ns ns ns ns ns % %
OVFL to LRCK edge setup time OVFL to LRCK edge hold time OVFL time-out on overrange condition Fs = 44.1, 88.2, 176.4kHz Fs = 48, 96, 192kHz MCLK Specifications MCLK Period MCLK Pulse Width High MCLK Pulse Width Low Master Mode SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle SCLK Output Frequency Slave Mode Single Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge Double Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge Quad Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge
Fs tsclkw tsclkhl tdss tslrd Fs tsclkw tsclkhl tdss tslrd Fs tsclkw tsclkhl tdss tslrd
2 40 163 20 -20 50 40 163 20 -20 100 40 81 20 -10
50 50 50 -
50 60 40 20 100 60 40 20 192 60 20 10
kHz % ns ns ns ns kHz % ns ns ns ns kHz % ns ns ns ns
18
CS5361
t sclkh t sclkl SCLK input
SCLK output t msl r
t sl rd LRCK input
t sclkw
LRCK output
t sd o SDOUT MSB MSB-1
SDOUT
t lrdss MSB MSB-1
t dss MSB-2
Figure 16. Master Mode, Left Justified SAI
Figure 17. Slave Mode, Left Justified SAI
t sclkh t sclkl SCLK input
t mslr LRCK output
t sdo
SCLK output
t sclkw LRCK input t dss
SDOUT
MSB
SDOUT
MSB
MSB-1
Figure 18. Master Mode, I2S SAI
Figure 19. Slave Mode, I2S SAI
LRCK t setup OVFL t hold
Figure 20. OVFL Output Timing
19
CS5361
LRC K
L eft C h a n n e l
R ig h t C h a n n e l
SCLK
SD ATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 2 2
Figure 21. Left Justified Serial Audio Interface
LR C K
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
SDATA
2 3 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 22. I2S Serial Audio Interface
LRCK
SCLK
OVFL
OVFL_R
OVFL_L
OVFL_R
Figure 23. OVFL Output Timing, I2S Format
LRCK
SCLK
OVFL
OVFL_R
OVFL_L
OVFL_R
Figure 24. OVFL Output Timing, Left-Justified Format
20
CS5361
5 PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
21
CS5361
6 PACKAGE DIMENSIONS
24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0 8
22
CS5361
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1 SEATING PLANE A
E b2 SIDE VIEW
123
L
e
END VIEW
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4 MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8 MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4 MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8
NOTE
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
23
CS5361
7 ADDENDUM
The CS5351 and CS5361 family of analog-to-digital converters are functionally compatible and can easily be interchanged with minimal modifications to the input buffer circuitry. Figure 25 shows an analog input buffer that provides anti-alias filtering, proper dc biasing, and optimum source impedance for the modulators. The input buffer shown will work well with both the CS5351 and the CS5361, merely by changing the bill of materials. In order to use this buffer design with the CS5351, one would stuff the 0ohm resistors R19 and R22 and not populate R3 and R20. This will create a single-ended input buffer with the unused differential input pin connected to the quiescent voltage of the converter (VQ). Note that in this configuration, it is unnecessary to have the second op-amp and related components. In order to use this buffer design with the CS5361, one would stuff the 0ohm resistors R3 and R20 and not populate R19 and R22. This will create a fully differential analog input buffer (as shown in Figure 3).
Figure 25. CS5351/CS5361 Analog Input Buffer
24

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